Celero Communications secured $275 million in a Series C financing round, bringing total capital raised to $415 million and valuing the company at more than $3 billion. The same announcement confirmed the validation of the industry’s first 2nm coherent digital signal processing (DSP) silicon, a step that could reshape AI‑focused optical interconnects.
Funding details and investor roster
The $275 million Series C round was announced on 8 September 2026 in Irvine, Calif. The round was led by Atreides Management, Valor Equity Partners and CapitalG. Existing investors Sutter Hill Ventures and Maverick Silicon also participated, underscoring continued confidence from the firm’s backers.
As part of the financing, Gavin Baker, Managing Partner and Chief Investment Officer at Atreides Management, will join Celero’s board of directors. The press release from the Financial Post (Business Wire) is the sole source for these specifics.
Capital totals and valuation
Prior to the new round, Celero had raised $140 million in earlier financing. Adding the $275 million Series C lifts cumulative capital to $415 million, all reported for the calendar year 2026. The same filing states that the financing values Celero at more than $3 billion, also measured in 2026 USD.
| Metric | Amount | Currency | Period |
|---|---|---|---|
| Series C funding | 275 million | USD | 2026 |
| Total capital raised | 415 million | USD | 2026 |
| Company valuation (minimum) | 3 billion | USD | 2026 |
Source: Financial Post (Business Wire press release).
Technology breakthrough: 2nm coherent DSP silicon
The same announcement highlighted successful validation of the industry’s first 2nm coherent DSP silicon. The validation covered both DSP processing and advanced analog technology, establishing a scalable foundation for next‑generation AI optical interconnects.
According to the release, the new silicon enables higher‑bandwidth, lower‑power connectivity ranging from 1.6 Tb/s through 3.2 Tb/s. Those figures are presented as the performance envelope for hyperscale AI clusters and cloud data centres, indicating that the chip can sustain double‑the‑current‑throughput levels while consuming less power per bit.
Higher‑bandwidth, lower‑power optical links are a critical need as AI workloads scale. By moving to a 2nm process node, Celero’s coherent DSP silicon promises to reduce power consumption per terabit of data transferred, a metric that data‑centre operators watch closely when planning upgrades.
The financing is earmarked to accelerate Celero’s product roadmap, fund additional research and development, and move the technology toward production readiness. While the press release does not disclose a specific production timeline, the language suggests that the company expects to meet growing demand for AI‑centric optical connectivity in the near term.
What remains unknown
- The exact number of chips that will enter volume production has not been disclosed.
- Pricing for the 2nm coherent DSP silicon, and how it compares with existing 3nm or 5nm solutions, is not provided.
- Details on the geographic rollout of the technology—whether it will be limited to North America first or have a broader global launch—are absent.
These gaps leave investors and potential customers waiting for further updates from Celero.
Context within the AI‑optics market
Celero’s announcement arrives amid a wave of capital inflows to AI‑focused semiconductor firms. While other recent stories have covered large financing rounds at companies such as Mistral AI and Crusoe, Celero’s combination of a sizable Series C and a concrete technology validation differentiates it from pure‑play funding news.
For readers tracking AI‑infrastructure spend, the key takeaway is that Celero now has both the financial backing and a validated 2nm coherent DSP platform to compete for contracts that demand the highest bandwidth per watt. The company’s valuation exceeding $3 billion reflects market belief that such capabilities will be monetised quickly as hyperscale operators upgrade their interconnect layers.
Future reporting will focus on any announced customer wins, production milestones, and how the 2nm DSP silicon performs in real‑world data‑centre deployments.